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[VHDL-FPGA-Verilog] testbench

Description: VHDL和verilog的TESTBENCH 编写方法。非常好的资料。英文的,但很简单。-Written in VHDL-TESTBENCH. Very good information. In English, but very simple.
Platform: | Size: 497664 | Author: 赵峰 | Hits:

[Software Engineering] A-Verilog-HDL-Test-Bench-Primer

Description: 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed description of how to use Verilog language Testbench file
Platform: | Size: 57344 | Author: | Hits:

[VHDL-FPGA-Verilog] labs_system_verilog_testbench

Description: system verilog testbench 对应代码。-labs for system verilog testbench
Platform: | Size: 71680 | Author: 李倩 | Hits:

[Other] System_Verilog_Tutorial

Description: System Verilog Testbench Tutorial
Platform: | Size: 2405376 | Author: 龙川 | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[Crack Hack] Testbench

Description: 这是一段verilog的调用测试例子，可以以此作为参考，对其他verilog仿真时，进行调用。-This is a verilog call the test example, can be used as a reference, on the other Verilog simulation call.
Platform: | Size: 1024 | Author: 达到 | Hits:

[VHDL-FPGA-Verilog] matlab-and-verilog-fir4_3

Description: 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Platform: | Size: 8192 | Author: 李静 | Hits:

[VHDL-FPGA-Verilog] testbench_learn

Description: 自己写的一个移位寄存器的实例，该例子主要用来讲述verilog中的testbench的写作，以及在testbench中怎样使用task，以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to make the simulation more simple and efficient
Platform: | Size: 3072 | Author: 雷 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
Platform: | Size: 52224 | Author: 程硕 | Hits:

[Other] shift-register-and-testbench

Description: Shift register and testbench in verilog
Platform: | Size: 1024 | Author: pravat | Hits:

[VHDL-FPGA-Verilog] xuliejianceqi

Description: 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
Platform: | Size: 174080 | Author: xuzehao | Hits:

[VHDL-FPGA-Verilog] ADF4113_loader

Description: ADF4113 loader written on Verilog + Icarus Verilog testbench
Platform: | Size: 11264 | Author: SigSig | Hits:

[VHDL-FPGA-Verilog] serial-cordic-verilog

Description: implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
Platform: | Size: 3072 | Author: appolo | Hits:

[VHDL-FPGA-Verilog] Verilog-code-for-finding-GCD

Description: State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
Platform: | Size: 1024 | Author: sumeshp1 | Hits:

[Other] sv_lab_switch

Description: system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
Platform: | Size: 11264 | Author: mayunli | Hits:

[Other] gen_tb

Description: 自己写的perl程序，可以根据逻辑代码的top文件自动生成verilog的testbench，方便做simulation，提高效率-perl program,written by myself, can automatically generate verilog testbench according to the logic of the code top file, easy to do simulation, improve efficiency
Platform: | Size: 1024 | Author: derek | Hits:

[VHDL-FPGA-Verilog] 64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc

Description: 64Bit Look Ahead Adder Verilog Code with Testbench
Platform: | Size: 2048 | Author: Anand | Hits:

[VHDL-FPGA-Verilog] DES-Verilog-master

Description: DES加密算法硬件verilog实现，包含testbench，加密主模块encrypt，明文变换模块LRToCiphertextConverter，NextRi模块等子模块。-DES encrypt verilog
Platform: | Size: 11264 | Author: lv | Hits:

[Other] testbench.sv

Description: RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；--RS Coding and Decoding Verilog code，　implement RS（544,514)
Platform: | Size: 4096 | Author: liuchao | Hits:

[VHDL-FPGA-Verilog] pipeline_add

Description: pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
Platform: | Size: 4096 | Author: adfadf | Hits:
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